PIC18F4423-I/ML【PDF 22/54 页】IC PIC MCU FLASH 8KX16 44QFN

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Sheet目录3831

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2009 Microchip Technology Inc.

DS39755C-page 29

PIC18F2423/2523/4423/4523

The value in the ADRESH:ADRESL registers is

unknown following POR and BOR Resets and is not

affected by any other Reset.

After the A/D module has been configured as desired,

the selected channel must be acquired before the

conversion is started. The analog input channels must

have their corresponding TRIS bits selected as inputs.

To determine acquisition time, see Section 2.1 “A/D

Acquisition Requirements”.

After this acquisition time has elapsed, the A/D conver-

sion can be started. An acquisition time can be

programmed to occur between setting the GO/DONE

bit and the actual start of the conversion.

The following steps should be followed to perform an A/D

conversion:

Configure the A/D module:

Configure analog pins, voltage reference and

digital I/O (ADCON1)

Select A/D input channel (ADCON0)

Select A/D acquisition time (ADCON2)

Select A/D conversion clock (ADCON2)

Turn on the A/D module (ADCON0)

Configure the A/D interrupt (if desired):

Clear ADIF bit

Set ADIE bit

Set GIE bit

Wait the required acquisition time (if required).

Start conversion by setting the GO/DONE bit

(ADCON0<1>).

Wait for the A/D conversion to complete by either:

Polling for the GO/DONE bit to be cleared

Waiting for the A/D interrupt

Read the A/D Result registers (ADRESH:ADRESL)

and clear the ADIF bit, if required.

For the next conversion, go to step 1 or step 2,

as required.

The A/D conversion time per bit is defined as

TAD. A minimum wait of 2 TAD is required before

the next acquisition starts.

FIGURE 2-2:

A/D TRANSFER FUNCTION

FIGURE 2-3:

ANALOG INPUT MODEL

Dig

ita

lCo

utp

FFEh

003h

002h

001h

000h

1LS

2LS

094

3LS

Analog Input Voltage

FFFh

095

VAIN

CPIN

ANx

5 pF

VT = 0.6V

ILEAKAGE

RIC

≤ 1k

Sampling

Switch

RSS

CHOLD = 25 pF

VSS

VDD

±100 nA

Legend: CPIN

ILEAKAGE

RIC

CHOLD

= Input Capacitance

= Threshold Voltage

= Leakage Current at the pin due to

= Interconnect Resistance

= Sampling Switch

= Sample/Hold Capacitance (from DAC)

various junctions

= Sampling Switch Resistance

RSS

VDD

Sampling Switch

Ω)

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